Enhancing the Filtering Capability and the Dynamic Performance of a Third-Order Phase-Locked Loop under Distorted Grid Conditions

This work proposes a structural enhancement and new technique to design the loop filter (LF) of third-order phase-locked (PLL) enhance PLL dynamic performance under abnormal grid conditions. The proposed combines moving average (MAF) an arbitrarily delayed signal cancelation (ADSC) for achieve DC-offset rejection harmonics elimination. window length MAF is selected be one-sixth fundamental period remove non-triple odd speed up response. triple are eliminated, adopting line-to-line voltage concept, while ADSC operator rejects DC offset. LF based on modified polynomial tuned using stochastic optimization minimize settling time frequency deviation, offering better over symmetrical optimum method (SOM) achieving synchronization within one cycle. mathematical model, small-signal discussed. Finally, verified numerically experimentally with comparisons other PLLs demonstrate effectiveness work.